Introduction
　　For years, EDA industry experts have warned that as designs get more complex, the process of verifying these designs will be very expensive and time consumingCONTROL ENGINEERING China版权所有, and in MAny cases more complex than the very designs being verified. In the past few years, high-performance embedded systems for controls, signal processing and communications applications have delivered on the first part of the warningCONTROL ENGINEERING China版权所有, complexityCONTROL ENGINEERING China版权所有, driven by the trend to miniaturize designs, and by the trend to integrate multiple functional units into a single device. To counter this Increasing complexityCONTROL ENGINEERING China版权所有, designers are adopting "design to test" methodology, and benefiting from a) bit-true simulation of Model-Based Design executable models to identify and fix flaws during design; b) automatic code generation to quickly prototype designs; and more recently c) utilizing the original executable models to directly validate final implementations through cosimulation. This article focuses on the third benefitCONTROL ENGINEERING China版权所有, namely utilizing the original executable models for verification and validationCONTROL ENGINEERING China版权所有, and shows that system-level verification through cosimulation is now a proven way to validate and verify RTL implementations. Fast bidirectional cosimulation interfaces between higher-level system design environments and high-performance HDL simulators make this possible.