Introduction
For years控制工程网版权所有, EDA industry experts have warned that as designs get more complexCONTROL ENGINEERING China版权所有, the process of verifying these designs will be very expensive and time consuming, and in MAny cases more complex than the very designs being verified. In the past few years控制工程网版权所有, high-performance embedded systems for controls, signal processing and communications applications have delivered on the first part of the warningwww.cechina.cn, complexity, driven by the trend to miniaturize designs, and by the trend to integra
te multiple functional units into a single device. To counter this Increasing complexity, designers are adopting "design to test" methodology, and benefiting from a) bit-true simulation of Model-Based Design executable models to identify and fix flaws during design; b) automatic code generation to quickly prototype designs; and more recently c) utilizing the original executable models to directly validate final implementations through cosimulation. This article focuses on the third benefit, namely utilizing the original executable models for verification and validationCONTROL ENGINEERING China版权所有, and shows that system-level verification through cosimulation is now a proven way to validate and verify RTL implementations. Fast bidirectional cosimulation interfaces between higher-level system design environments and high-performance HDL simulators make this possible.
For years控制工程网版权所有, EDA industry experts have warned that as designs get more complexCONTROL ENGINEERING China版权所有, the process of verifying these designs will be very expensive and time consuming, and in MAny cases more complex than the very designs being verified. In the past few years控制工程网版权所有, high-performance embedded systems for controls, signal processing and communications applications have delivered on the first part of the warningwww.cechina.cn, complexity, driven by the trend to miniaturize designs, and by the trend to integra
Verification: Number One Bottleneck
As overall design complexity increases, the task of design verification has grown proportionately.
In a recent article1, Dr. Horgan notes that “hardware verification has itself become more challenging. Verification times have increased with rising gate count and as overall design complexity grows. According to a survey by Collett International Research in 2002www.cechina.cn, only 39% of designs were bug-free at first silicon, while 60% contained logic or functional flaws. More than 20% required three or more silicon spins. A Collett survey also showed that nearly 50% of total engineering time was spent in verificati
As overall design complexity increases, the task of design verification has grown proportionately.
In a recent article1, Dr. Horgan notes that “hardware verification has itself become more challenging. Verification times have increased with rising gate count and as overall design complexity grows. According to a survey by Collett International Research in 2002www.cechina.cn, only 39% of designs were bug-free at first silicon, while 60% contained logic or functional flaws. More than 20% required three or more silicon spins. A Collett survey also showed that nearly 50% of total engineering time was spent in verificati


在线会议
论坛
专题
工控直播
新闻中心
子站
技术
社区


福禄克六大“法宝”帮您搞定过程仪表校准难题
中控时间序列大模型TPT免费有奖体验
爱德克SE2L进阶版安全激光扫描仪有奖预约演示
剑维软件电子半导体行业白皮书有奖下载
魏德米勒麒麟系列产品赋能本土工业



























